The Complementary Metal Oxide Semiconductor (CMOS) technology has been recognized as the leading technology for use in digital electronics in general and for use in many computer products in particular. This is because the Integrated Circuits (IC) formed on silicon wafers using CMOS technology have high density, operate at high speed and have a low standby power consumption. The basic building blocks of such integrated circuits are N-Channel and P-Channel type transistors. Despite these advantages, the CMOS technology has been associated with high sheet resistance in the source and drain regions of the transistors as well as in the polysilicon films frequently used to form the gate regions. This high sheet resistance is detrimental to the basic operations of the CMOS device, such as the speed and power consumption.
Self-aligned silicided (SALICIDED) metal oxide semiconductor techniques are frequently used to reduce the sheet resistance of a CMOS device thereby improving speed characteristics of the device. In this technique, a thin film of metal, such as Titanium (Ti), Cobalt (Co) etc., is reacted with the source, drain and polysilicon regions under specified environmental conditions. The thin film of metal is reacted with the silicon to form a layer of silicide. Thus, cobalt and titanium are reacted with silicon to form Cobalt Silicide (CoSi.sub.2) and Titanium Silicide (TiSi.sub.2) respectively. The silicide layer has a lower sheet resistance than the sheet resistance of silicon. During the manufacturing process, a silicide layer when formed at a low temperature prevents the formation of a silicide layer over silicon dioxide or silicon nitride, two extensively used insulating materials during the processing of semiconductor devices. Further, the unreacted metal film formed over oxide or silicon nitride can be etched using chemical wet agents without adversely affecting the silicide formed in the polysilicon and silicon regions. Cobalt Silicide (CoSi.sub.2) is generally preferred because of its resistance to attack by wet chemical etching agents like Hydrofluoric Acid (HF), and its low affinity to adhere to oxides in the field oxide region (Isolation region) or the spacer region (Transistor region).
To prevent electrical shorting of adjacent silicided regions, i.e., the source, gate and drain regions, prior art processes utilize oxide (Silicon Dioxide-SiO.sub.2) spacers to isolate these regions. Depending on the design rules, process requirements, tolerances, junction width, junction depth, spacer width, etc., the SALICIDED CMOS process, however, has resulted in increased manufacturing process steps. Among them are a separate masking and implant of a dopant (a conductivity-type impurity) in the source, drain and gate regions of one type of Transistor (N-channel), followed by the masking add implant of a dopant in the source, drain and gate regions of the second type Transistor (P-channel). This is followed by the spacer formation, Reactive Ion Etch (RIE) to selectively etch the insulating materials. The next step is to again mask the P-channel transistor and ion implant the N-type dopant. This is again followed by masking the N-channel transistor and implanting the P-type dopant to obtain adequate junction depths. This is then followed or preceded by the formation of a silicide layer. This process could result in a total of four masking steps and four ion implant steps to form the CMOS (N-channel and P-Channel) Transistors.
Previous attempts to reduce the number of masking steps and the number of implants have included utilizing oxide spacers having a thickness of less than 600 Angstroms (.ANG.) Use of such thin spacers enables the source and drain dopant diffusion final depth to completely overlap tee polysilicon region, thereby reducing the sheet resistance of the source and drain regions and thus improving the threshold voltage control of each Transistor. The use of such thin spacers creates repeatability and controlability problems during the deposition and etching steps of the manufacturing process.
The instant invention discloses a method of forming a very thin oxide spacer by utilizing a disposable nitride (Silicon Nitride-Si.sub.3 N.sub.4) space. This method of the invention reduces the number of steps during the manufacturing of a SALICIDED CMOS device from four masking steps (two masking steps each for N & P-channel Transistors) and four dopant implants (two implants each for N & P Transistors) to two masking steps (one for P-channel and one for N-channel Transistors) and two dopant implants (one for N and one for P-channel Transistors). The method of the invention is especially useful when smaller and shallower source and drain regions are desired. The method further enables one to form very shallow source and drain regions which completely surround the silicide layer and completely overlap the polysilicon gate region.